This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to packaging for integrated circuits.
Some types of integrated circuits are completely custom designed, where each of the electrical devices in the integrated circuit is specifically selected for the custom design, and the integrated circuit is laid out in a customize manner. Such integrated circuits tend to have a relatively large amount of overhead associated with them. For example, there is a large amount of design work involved in producing such a customized integrated circuit. Further, customized mask sets and tooling are required to produce the integrated circuits. When it is expected that a very large number of the integrated circuits will be sold, then it can be cost effective to invest in the overhead associated with the customized integrated circuit, as the overhead can be paid off over a large number of the integrated circuits.
However, there are other applications where such a large number of sales of the integrated circuit is not expected. In these applications, it tends to be cost prohibitive to design the integrated circuit from scratch, so to speak, and to invest in completely customized mask sets and tooling, because there will not be enough of the integrated circuits fabricated to justify such a large investment.
For these smaller-number applications, a different type of integrated circuit is commonly used, called an application specific integrated circuit, or ASIC. ASICs are designed using standardized design elements, or modules, which are combined in a desired configuration to support the intended application. In other words, the design of the integrated circuit is application-specific, as the name implies. ASICs tend to be much cheaper to design and produce than custom integrated circuits, because the standardized design elements have already been designed. Further, mask designs already exist for the design elements. Thus, there is a tremendous head-start on the design process, and ASICs therefore tend to be much less expensive to fabricate than completely customized integrated circuits.
Unfortunately, because the standardized design elements of an ASIC can be combined in a variety of ways, the cost savings associated with standardization have typically not been extended to the packaging used for the ASICs, or the printed circuit boards to which they are ultimately mounted. For example, because different ASICsxe2x80x94even those using similar standardized modulesxe2x80x94tend to be laid out with the standardized modules in different configurations, the package substrate and printed circuit board typically require a different configuration for each such design. Thus, all the costs of a completely customized package design tend to be incurred, even when using standardized modules in an ASIC design.
What is needed, therefore, are package substrate and printed circuit board designs with standardized elements for use with an ASIC, which designs can help reduce the costs associated with designing packages and circuit boards for different ASICs.
The above and other needs are met by a package substrate adapted to receive an integrated circuit. The package substrate includes an upper contact layer, a transmitter power layer, a transmitter ground layer, a transmitter routing layer disposed between the transmitter power layer and the transmitter ground layer, a receiver power layer, a receiver ground layer, a receiver routing layer disposed between the receiver power layer and the receiver ground layer, and a lower contact layer.
Electrically conductive contacts are disposed in transceiver core contact patterns on the upper contact layer, and are adapted to make electrical connections with the integrated circuit. Each of the transceiver core contact patterns includes several different kinds of contacts, as described below.
Two transmitter signal contacts are disposed in a transmitter signal contact differential pair adapted to conduct transmitter signals. Two receiver signal contacts are disposed in a receiver signal contact differential pair adapted to conduct receiver signals. Transmitter power contacts are disposed in a transmitter power contact group and adapted to provide power for only the transmitter signals conducted by the transmitter signal contact differential pair. Receiver power contacts are disposed in a receiver power contact group and adapted to provide power for only the receiver signals conducted by the receiver signal contact differential pair. Ground contacts are adapted to provide ground for both the transmitter signals and the receiver signals.
Electrically conductive transmitter signal traces are disposed in transmitter signal trace differential pairs on the transmitter routing layer. Electrically conductive transmitter signal vias are disposed in transmitter signal via differential pairs, which electrically connect the transmitter signal trace differential pairs with the transmitter signal contact differential pairs.
Electrically conductive transmitter power planes are disposed on the transmitter power layer, and electrically conductive transmitter power vias electrically connect the transmitter power planes with the transmitter power contact groups. Electrically conductive transmitter ground vias electrically connect the transmitter ground layer with the ground contacts.
A given one of each of the transmitter power planes is associated with and aligned with a given one of each of the transmitter signal trace differential pairs. The association is based on the given one of the transmitter power planes and the given one of the transmitter signal trace differential pairs being electrically connected to contacts disposed within a single one of the transceiver core contact patterns.
Similarly, electrically conductive receiver signal traces are disposed in receiver signal trace differential pairs on the receiver routing layer. Electrically conductive receiver signal vias are disposed in receiver signal via differential pairs, and electrically connect the receiver signal trace differential pairs with the receiver signal contact differential pairs.
Electrically conductive receiver power planes are disposed on the receiver power layer, and electrically conductive receiver power vias electrically connect the receiver power planes with the receiver power contact groups. Electrically conductive receiver ground vias electrically connect the receiver ground layer with the ground contacts.
A given one of each of the receiver power planes is associated with and aligned with a given one of each of the receiver signal trace differential pairs. The association is based on the given one of the receiver power planes and the given one of the receiver signal trace differential pairs being electrically connected to contacts disposed within a single one of the transceiver core contact patterns.
Lower electrical contacts are disposed on the lower contact layer and are electrically connected to the transmitter signal traces, the transmitter power planes, the transmitter ground layer, the receiver signal traces, the receiver power planes, and the receiver ground layer. None of the receiver signal traces in the package substrate are disposed on the transmitter routing layer and none of the transmitter signal traces in the package substrate are disposed on the receiver routing layer.
In this manner, none of the differential transmitter trace pairs are on the same layer as, nor can they interfere with the differential receiver trace pairs. Further, each differential trace pair, whether they be for receiver signals or transmitter signals, is isolated by a ground plane on one side, and a dedicated power plane on the other side, which power plane the trace pair does not share with any other trace pair. Thus, the package substrate is cross-talk tolerant to very high speed core devices. Thus, a package substrate according to the present invention has standardized transceiver contact patterns and routing layers, which can be used with a wide variety of different ASIC designs, thereby lowering the costs associated with packaging the different ASIC devices.
In various preferred embodiments, the transmitter routing layer is disposed above the receiver routing layer. The transmitter power layer is preferably disposed below the transmitter routing layer and the transmitter ground layer is preferably disposed above the transmitter routing layer. In one embodiment, there is a second transmitter ground layer disposed beneath the transmitter power layer. Preferably the receiver power layer is disposed below the receiver routing layer and the receiver ground layer is disposed above the receiver routing layer. In one embodiment, there is a second receiver ground layer disposed below the receiver power layer.
A packaged integrated circuit including an integrated circuit and the package substrate described above is also described herein.